The linearity or Spurious-Free Dynamic Range (SFDR) of analog-to-digital converters (ADCs) has been steadily improving as a result of increasing demands from various applications and communication infrastructure. Several techniques have been developed to improve the linearity of ADCs. However, they have limitations that restrict their use.
Analog to digital conversion of signals involves two different operations. The first operation, called sampling, converts an input signal from a time continuous signal to a time discrete signal. The second operation, called quantization, converts the sampled signal into a finite number of values. Nonlinearities in an ADC can arise in both the sampling and quantization operations. The Sampler used for sampling, particularly the input stage of the Sampler, can introduce nonlinearities. Non-uniform distribution of the quantization levels of the Quantizer used for quantization can also introduce nonlinearities.
Good linearity can be achieved by proper design methodologies and circuit optimization. However, at a certain level, a limit is reached due to weaknesses in process technologies or due to random mismatches. In addition, the power dissipation may be unacceptably high using a straightforward approach. Therefore, different methods have been implemented to improve linearity without the above drawbacks. Two common methods are calibration and dithering.
Nonlinearities in the Quantizer are generated if the quantization levels are not evenly distributed in the entire signal range of the Quantizer. The non-uniform distribution of quantization levels is often due to effects like mismatch, incomplete transient settling, low amplifier gain, and signal dependent gain in amplifiers. Calibration algorithms can be used where the quantization steps are measured, and errors can be corrected either in the analog or digital domain.
With dithering, a small random voltage, called dither signal, is added to or multiplied with the input signal before it is propagated through the signal chain. The dither signal, which typically is spectrally white, mixes with the input signal and error terms, transforming the spurious components into spectrally white noise contributions. Dithering can improve SFDR both due to nonlinearities in the Sampler and the Quantizer. However, it can improve performance only for circuitry behind the point in the signal chain where the dither is applied.
Both calibration and dithering are widely used in the industry both at the component level and the system level. There are however significant challenges with both methods.
With respect to calibration, measuring an error before correcting for it is required for all types of calibration. This must be done with extremely high accuracy. In an ADC, the SFDR typically will be around 20 dB better than the signal-to-noise ratio (SNR). In order to improve the SFDR beyond this value, the errors must be measured with significantly better accuracy than the SNR requirement plus 20 dB. On the other hand, if one could use dither and convert a tone 20 dB below SNR to white noise, the SNR would not be significantly affected. Hence, a significant challenge of calibration is to be able to measure or estimate the errors with sufficient accuracy.
In practice, calibration schemes will add significant complexity to the design. Designing the calibration circuitry and system can prove more difficult and time consuming than designing the ADC itself.
In addition, temperature and supply voltage variations require periodic recalibration. Many of the calibration schemes require that the ADC is disconnected from the signal path during the calibration procedure. This will introduce an interruption in the operation of the ADC that is undesirable in many applications.
Conventionally used dithering techniques also have limitations. A dither signal will has the same properties as noise, and will add to the noise power in the signal, reducing the SNR. It is therefore common to use techniques to digitally subtract the dither signal from the digital output of the ADC. This can be done only with certain accuracy, and a reduction in SNR due to “leakage” of dither noise into the signal is common.
Another problem with dithering is that the total power (or amplitude) converted by the ADC is increased by the amplitude of the dither signal. To avoid saturation of the ADC, the input signal amplitude therefore has to be reduced by the same amount as the dither signal amplitude. However, reducing the input signal amplitude is equivalent to reducing the SNR of the ADC since the noise power is kept constant. The dither signal is most efficient when the amplitude of the dither signal is relatively large compared with the signal. This introduces a tradeoff between improvement in SFDR and reduction in SNR due to the dither signal.